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E2U0042-28-81
Semiconductor MSM7705-01/02/03
Semiconductor 4ch Single Rail CODEC
This version: Aug. 1998 MSM7705-01/02/03 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7705-01/02/03 are four-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices contain four-channel A/D and D/A converters in a single chip and achieve a reduced footprint and a reduced number of external components. The MSM7705-01/02/03 are best suited for digital telephone terminals, digital PABXs, and pushbutton phones.
FEATURES
* Single power supply: +5 V * Power consumption Operating mode: 70 mW Typ. 140 mW Max. Power-saving mode: 14 mW Typ. 32 mW Max. Power-down mode: 0.05 mW Typ. 0.3 mW Max. * Conforms to ITU-T Companding law MSM7705-01: m/A-law pin-selectable MSM7705-02: m-law MSM7705-03: A-law * Built-in PLL eliminates a master clock * The PCM interface can be switched between 4 channel serial/parallel * Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544 kHz (During 4 channel serial mode, the 64, 96, 128, and 192 kHz clocks are disabled) * Transmit gain adjustable for each channel * Built-in reference voltage supply * Analog output can directly drive a 600 W line transformer * Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name : MSM7705-01GS-2K) (Product name : MSM7705-02GS-2K) (Product name : MSM7705-03GS-2K)
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MSM7705-01/02/03
BLOCK DIAGRAM
AIN1 GSX1 AIN2 GSX2
- +
RC LPF
8th BPF
AD CONV. TCONT
DOUT1 DOUT2 DOUT3 DOUT4
- +
RC LPF
8th BPF AUTO ZERO PLL XSYNC BCLK (ALAW) CHPS
AIN3 GSX3 AIN4 GSX4
- +
RC LPF
8th BPF
AD CONV.
- +
RC LPF
8th BPF AUTO ZERO
AOUT1
- +
5th LPF
RTIM S&H DA CONV.
RSYNC
AOUT2
- +
5th LPF
S&H RCONT DIN1 DIN2 DIN3 DIN4
AOUT3
- +
5th LPF
S&H DA CONV.
AOUT4
- +
5th LPF
S&H PWD Logic PDN VDD AG DG
SGC
SG GEN
VR GEN
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PIN CONFIGURATION (TOP VIEW)
NC 1 NC 2 NC 3
(V
VDD 4
DD
5
NC 6 NC 7 DIN4 8 DIN3 9 DIN2 10 DIN1 11
43 AOUT3 42 AOUT2 41 AOUT1 36 GSX4 37 AIN4 38 SGC 40 AG 39 AG
MSM7705-01/02/03
44 AOUT4
35 GSX3
34 AIN3
33 AIN2 32 GSX2 31 GSX1 30 AIN1 29 NC 28 NC 27 NC 26 NC 25 (ALAW)* 24 PDN 23 CHPS
(
RSYNC 12
XSYNC 13
BCLK 14
NC 15
( DG 17
DG 16
NC 18
DOUT4 19
DOUT3 20
DOUT2 21
NC : No connect pin 44-Pin Plastic QFP
VDD, DG, and AG have two pins each. Each of these pairs are internally connected with each other. * The ALAW pin is only supported by MSM7705-01GS-2K.
DOUT1 22
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PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, AIN3, AIN4, GSX1, GSX2, GSX3, GSX4 AIN1, AIN2, AIN3, and AIN4 are the transmit analog inputs for channels 1, 2, 3 and 4 respectively. GSX1, GSX2, GSX3, and GSX4 are the transmit level adjustments for channels 1, 2, 3 and 4 respectively. AIN1, AIN2, AIN3, and AIN4 are connected to the inverting inputs for the op-amps. GSX1, GSX2, GSX3, and GSX4 are connected to the outputs for the op-amps. They are used to adjust levels as shown below, and are connected to the outputs of the op-amps. During power saving mode and power down mode, the GSX1, GSX2, GSX3, and GSX4 outputs are at 0 V. When these pins are not used, connect AIN1 to GSX1, AIN2 to GSX2, AIN3 to GSX3, and AIN4 to GSX4.
R2n CHn Analog Input C1n R1n
GSXn AINn - +
CHn Gain Gain = R2n/R1n 10 R1n: Variable R2n > 20 kW C1n > 1/(2 3.14 30 R1n) (F)
AOUT1, AOUT2, AOUT3, AOUT4 AOUT1, AOUT2, AOUT3, and AOUT4 are the receive filter outputs for channels 1, 2, 3, and 4 respectively. When the digital signal of +3 dBm0 is input to DIN1, DIN2, DIN3, and DIN4, the output signal has an amplitude of 3.4 VPP above and below the signal ground voltage (SG : 1/2 VDD). The output can drive a load of 600 W or more. During power saving or power down mode, these outputs are at the voltage level of SG with a high impedance.
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Semiconductor DIN1, DIN2, DIN3
MSM7705-01/02/03
PCM signal inputs for channels 1, 2, and 3 when the parallel mode is selected. D/A conversion is performed by the serial PCM signals to these pins, the RSYNC signals synchronous with the serial PCM signals, and the BCLK signal. Then the analog signals are output from AOUT1, AOUT2, and AOUT3 pins, respectively. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is not used and should be connected to GND (0 V). DIN4 PCM signal input for channel 4 when the parallel mode is selected. D/A conversion is performed by the serial PCM signal to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal. Then the analog signal is output from AOUT4 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is used for the 4ch multiplexed PCM signal input. BCLK Shift clock signal input for DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, DOUT3, and DOUT4. The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight bits of PCM data required are selected from a series of PCM signal to the DIN1, DIN2, DIN3, and DIN4 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as BCLK). The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, this device operates in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics specified in the data sheet are not guaranteed.
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MSM7705-01/02/03
Transmit synchronizing signal input. PCM output signal from the DOUT1, DOUT2, DOUT3, and DOUT4 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz 50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, this device can be operated in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state. DOUT1 PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is configured to be the output of serial multiplexed 4ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7705-03 (A-law) outputs the character signal, inverting the even bits.
PCMIN/PCMOUT MSM7705-02 (m-law) MSD +Full scale +0 -0 -Full scale 1000 1111 0111 0000 0000 1111 1111 0000 MSM7705-03 (A-law) MSD 1010 1101 0101 0010 1010 0101 0101 1010
Input/Output Level
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DOUT2, DOUT3, DOUT4 PCM signal outputs for channels 2, 3, and 4 when parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is unconnected. A pull-up resistor must be connected to each of these pins because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7705-03 (A-law) outputs the character signal inverting the even bits. CHPS Control signal input for the mode selection of PCM input and output. When this signal is at a logic "1" level, the PCM input and output are in parallel mode. The PCM data of CH1, CH2, CH3, and CH4 is input to DIN1, DIN2, DIN3, and DIN4 outputs from DOUT1, DOUT2, DOUT3, and DOUT4 with the same timing. When this signal is at logic "0" level, the PCM input and output are in serial mode. The PCM data of CH1 to CH4 is input from DIN4 and output from DOUT1 as time division multiplexed data. PDN Power down control signal. When PDN is at a logic "0" level, both transmit and receive circuits are in power down state. VDD Power supply for +5 V. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 mF to 1 mF with excellent high-frequency characteristics and a capacitor of 10 mF to 20 mF should be connected between this pin and the AG pin if needed. AG Analog signal ground. DG Ground for digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground.
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MSM7705-01/02/03
Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Only the MSM7705-01GS-2K has this pin. The CODEC will operate in the m-law when this pin is at a logic "0" level and will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since this pin is internally pulled down.
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition
-- -- -- --
Rating 0 to 7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150
Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage Symbol VDD Ta VAIN VIH VIL Gain = 1 XSYNC, RSYNC, BCLK, DIN1, DIN2, DIN3, DIN4, PDN, CHPS, ALAW BCLK = (When in 4ch serial Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width DIN Setup Time DIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width FC FS DC tIr tIf tXS tSX tRS tSR tWS tDS tDH RDL CDL Voff -- mode, 64, 96, 128, 192 kHz are not used) XSYNC, RSYNC BCLK XSYNC, RSYNC, BCLK, DIN1, DIN2, DIN3, DIN4, PDN, CHPS BCLKAEXSYNC, See Fig. 1 XSYNCAEBCLK, See Fig. 1 BCLKAERSYNC, See Fig. 1 RSYNCAEBCLK, See Fig. 1 XSYNC, RSYNC DIN1, DIN2, DIN3, DIN4 DIN1, DIN2, DIN3, DIN4
DOUT1, DOUT2, DOUT3, DOUT4
Condition Voltage must be fixed --
Min. 4.75 -30 -- 2.2 0
Typ. 5.0 +25 -- -- --
Max. 5.25 +85 3.4 VDD 0.8
Unit V C VPP V V
64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544 6.0 40 -- -- 100 100 100 100 1 BCLK 100 100 0.5 -- VDD/2 -10 -- 8.0 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10.0 60 50 50 -- -- -- -- 100 -- -- -- 100 VDD/2 +100 VDD/2 +10 500 kHz % ns ns ns ns ns ns ms ns ns kW pF mV mV ns kHz
Pull-up resistor --
Transmit gain stage, Gain = 1 VDD/2 -100 Transmit gain stage, Gain = 10 XSYNC, RSYNC
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ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = +5 V 5%, Ta = -30C to +85C) Parameter Symbol IDD1 IDD2 Condition Operating mode, No signal Power-save mode, PDN = 1, Power Supply Current XSYNC or BCLK OFF Power-down mode, PDN = 0 BCLK OFF -- -- -- -- Pull-up resistor > 500 W -- -- -- 2.6 6.0 mA Min. -- Typ. 14.0 Max. 28.0 Unit mA
IDD3 High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance VIH VIL IIH IIL VOL IO CIN
-- 2.2 0.0 -- -- 0.0 -- --
0.01 -- -- -- -- 0.2 -- 5
0.05 VDD 0.8 2.0 0.5 0.4 10 --
mA V V mA mA V mA pF
Transmit Analog Interface Characteristics
(VDD = +5 V 5%, Ta = -30C to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Gain = 1 Condition AIN1, AIN2, AIN3, AIN4 GSX1, GSX2, GSX3, GSX4 with respect to SG Min. 10 20 -- -1.7 -20 Typ. -- -- -- -- -- Max. -- -- 30 +1.7 +20 Unit MW kW pF V mV
Receive Analog Interface Characteristics
(VDD = +5 V 5%, Ta = -30C to +85C) Parameter Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RLAO CLAO VOAO VOSAO Condition Each output; AOUT1 with respect to SG AOUT2 -- AOUT3 RL = 0.6 kW; AOUT4 with respect to SG -- Min. 0.6 -- -1.7 -100 Typ. -- -- -- -- Max. -- 50 +1.7 +100 Unit kW pF V mV
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Semiconductor AC Characteristics
MSM7705-01/02/03
(VDD = +5 V 5%, Ta = -30C to +85C) Parameter Symbol Loss T1 Loss T2 Transmit Frequency Response Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Receive Frequency Response Loss R3 Loss R4 Loss R5 SD T1 SD T2 Transmit Signal to Distortion Ratio SD T3 SD T4 SD T5 SD R1 SD R2 Receive Signal to Distortion Ratio SD R3 SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 GT R2 Receive Gain Tracking GT R3 GT R4 GT R5 1020 1020 1020 1020 Freq. (Hz) 60 300 1020 2020 3000 3400 300 1020 2020 3000 3400 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -0.3 -0.5 -1.2 -0.3 -0.5 -1.2 -0.3 *1 *1 0 -0.15 -0.15 0.0 35 35 35 29 24 36 36 36 30 25 -0.3 0 Level Condition (dBm0) Min. 20 -0.15 -0.15 -0.15 0 -0.15 Typ. 26 +0.07 Reference -0.04 +0.03 0.40 -0.03 Reference +0.04 +0.11 0.47 43 41 38 31.5 27 43 41 40 33.5 30 +0.02 Reference +0.04 +0.15 +0.40 0.0 Reference +0.04 +0.16 +0.37 +0.3 +0.5 +1.2 dB +0.3 +0.5 +1.2 +0.3 dB +0.20 +0.20 0.80 -- -- -- -- -- -- -- -- -- -- +0.3 dB dB dB +0.20 +0.20 0.80 +0.20 Max. -- +0.20 dB Unit
*1 Psophometric filter is used
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Semiconductor AC Characteristics (Continued)
MSM7705-01/02/03
(VDD = +5 V 5%, Ta = -30C to +85C) Parameter Symbol Nidle T Nidle R AV T Absolute Level (Initial Difference) AV R AV Tt AV Rt 1020 0 VDD = 5 V 5% Ta = -30 to +85C A to A Absolute Delay tD tGD T1 tGD T2 Transmit Group Delay tGD T3 tGD T4 tGD T5 tGD R1 tGD R2 Receive Group Delay tGD R3 tGD R4 tGD R5 CR T Crosstalk Attenuation CR R CR CH 1020 0 1020 500 600 1000 2600 2800 500 600 1000 2600 2800
TRANS AE RECV RECV AE TRANS
Freq. (Hz) -- --
Idle Channel Noise
Level Condition (dBm0) AIN = SG -- *1 *2 -- *1 *3 VDD = 5.0 V Ta = 25C
Min. -- -- -- 0.821 0.821 -0.2 -0.2
Typ. -73.5 -71.5 -78 0.850 0.850 -- --
Max. -70 -68 -75 0.880
Unit
dBm0p
Vrms 0.880 +0.2 +0.2 dB dB
Absolute Level (Deviation of Temperature and Power)
0
BCLK = 64 kHz
-- -- --
-- 0.19 0.11 0.02 0.05 0.07 0.00 0.00 0.00 0.09 0.12 80 76 80
0.60 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 -- -- --
ms
0
*4
-- -- -- -- --
ms
0
*4
-- -- -- 75 70 75
ms
dB
CH to CH
*1 *2 *3 *4
Psophometric filter is used Upper columns are specified for the m-law, lower for the A-law Input "0" code to PCMIN Minimum value of the group delay distortion
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Semiconductor AC Characteristics (Continued)
MSM7705-01/02/03
(VDD = +5 V 5%, Ta = -30C to +85C) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio Symbol Freq. Level Condition (Hz) (dBm0) 4.6 kHz to 0 to 0 DIS 72 kHz 4000 Hz S IMD PSR T PSR R tSD Digital Output Delay Time tXD1 tXD2 tXD3 CL = 100 pF + 1 LSTTL 300 to 3400 fa = 470 fd = 320 0 to 50 kHz 0 -4 50 mVPP 4.6 kHz to 100 kHz 2fa - fd *5 Min. 30 -- -- -- 20 20 20 20 Typ. 32 -37.5 -52 30 -- -- -- -- Max. -- -35 -35 -- 200 200 200 200 ns Unit dB dBm0 dBm0 dB
*5 Measurement performed under idle channel noise
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Semiconductor
TIMING DIAGRAM
Transmit Timing
BCLK
tXS XSYNC DOUT1 DOUT2 DOUT3 DOUT4
Receive Timing
BCLK
tRS RSYNC DIN1 DIN2 DIN3 DIN4
BCLK XSYNC
, ,
1 2 3 tSX tWS tXD1 tSD MSD D2 1 2 3 tSR tWS tDS MSD D2
MSD MSD D2 D3 D4 D5 D6 D7 D8 CH1 PCM Data MSD MSD D2 D3 D4 D5 D6 D7 D8 CH1 PCM Data
MSM7705-01/02/03
4
5
6
7
8
9
10
11
tXD2 D3
D4
D5
D6
D7
tXD3 D8
Transmit Side
4
5
6
7
8
9
10
11
tDH D3 D4 D5 D6 D7 D8 Receive Side
Figure 1 Timing Diagram in the Parallel Mode (CHPS = 1)
MSD D2 D3 D4 D5 D6 D7 D8 CH2 PCM Data D2 D3 D4 D5 D6 D7 D8 CH3 PCM Data
MSD D2 D3 D4 D5 D6 D7 D8 CH4 PCM Data
DOUT1
Transmit Side BCLK RSYNC
MSD D2 D3 D4 D5 D6 D7 D8 CH2 PCM Data D2 D3 D4 D5 D6 D7 D8 CH3 PCM Data MSD D2 D3 D4 D5 D6 D7 D8 CH4 PCM Data
DIN4
Receive Side
Figure 2 Timing Diagram in the Serial Mode (CHPS = 0)
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APPLICATION CIRCUIT
Example of Basic Connection (PCM Serial Mode Operation)
+5 V CH1 Analog Input CH1 Analog Output CH2 Analog Input CH2 Analog Output CH3 Analog Input CH3 Analog Output CH4 Analog Input CH4 Analog Output 1 mF 20 kW 1 mF 20 kW MSM7705-01 AIN1 GSX1 AOUT1 1 mF 20 kW AIN2 GSX2 1 mF 20 kW AOUT2 DIN4 DIN3 DIN2 DIN1 BCLK XSYNC RSYNC PDN 4ch Multiplex PCM Signal Input 0V Bit Clock Input Sync Pulse Input Power Down Control Input 1 : Operation 0 : Power Down Companding Law Control Input 1 : A-law 0 : m-law DOUT1 DOUT2 DOUT3 DOUT4 1 kW 4ch Multiplex PCM (Open) Signal Output (Open) (Open)
1 mF 20 kW AIN3 GSX3 1 mF 20 kW AOUT3 1 mF 20 kW 1 mF 20 kW AIN4 GSX4 AOUT4 0.1 mF SGC AG AG DG DG CHPS VDD VDD 0V ALAW
0V +5 V 0 to 20 W 10 mF + 1 mF
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APPLICATION INFORMATION
DOUT Pull-up Resistor A value of the pull-up resistor for the DOUT pin should be determined depending on frequencies of BCLK and load capacitance. If a smaller value is used, there may be some degradation in noise performance, resulting in an increase in supply current. Equation to give pull-up resistor
1 -------- - 50 ns 4 fBCLK Rpull = ---------------- (W) CL where fBCLK = Frequency of BCLK CL = Load capacitance of the PCMOUT pin (approximately 20 pF for a CMOS or TTL load) 50 ns = Internal delay of the MSM7705
Condition for Calculation If data is turned back from DOUT to DIN under the condition the SYNC signal and BCLK signal rise simultaneously, the data can normally be transferred.
X, RSYNC
BCLK T T = Rpull CL DOUT
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Semiconductor Calculation Example for Typical Values
BCLK (kHz) 64 128 256 512 1024 1544 2048 Rpull (kW) CL = 10 pF 385.6 190.3 92.7 43.8 19.4 11.2 7.2 CL = 20 pF 192.8 95.2 46.3 21.9 9.7 5.6 3.6
MSM7705-01/02/03
CL = 50 pF 77.1 38.1 18.5 8.8 3.9 2.2 1.4
CL = 100 pF 38.6 19.0 9.3 4.4 1.9 1.1 0.7
Choice of Actual Resistor Value If the calculated value is more than or equal to 100 kW, 100 kW should be employed. +10% of the calculated value is within a tolerance, thus, for example, the value of 10 kW can be used for the calculated value of 9.3 kW in the above examples.
Channel Crosstalk The MSM7705 contains the 4-channel CODEC. The circuit and trace design and pin layout are made to minimize crosstalk between channels inside the LSI device provided the following should be taken into consideration. Transmit side The GSX1 - AIN2, AIN3, and AIN4 traces should not be kept closer. The GSX2 - AIN1, AIN3, and AIN4 traces should not be kept closer. The GSX3 - AIN1, AIN2, and AIN4 traces should not be kept closer. The GSX4 - AIN1, AIN2, and AIN3 traces should not be kept closer. AIN1, AIN2, AIN3, and AIN4, which are op-amp inverting input pins, have higher resistance, therefore proximity of these lines to signal lines of other channels may cause crosstalk. Receive side The channel outputs AOUT1, AOUT2, AOUT3, and AOUT4 of the receive side are amplifier outputs with lower resistance, thus crosstalk due to PCB traces is smaller. Nevertheless, the PCB traces should not be run closer together and in parallel wherever possible.
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How to Avoid Transmit Side Amplifier Oscillation Due to PCB Layout
AINn
- +
RF
GSXn
MSM7705
The trace length (illustrated by the bold line in the above drawing) should be kept as short as possible in order to avoid oscillation. The length of less than 2 cm or 3 cm is permissible, though it depends on PCB layout. It is recommended to connect a capacitor of 20 pF to 50 pF across the feedback resistor RF, if the oscillation occurs.
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NOTES ON USED
* To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance. * Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket. * When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latchup that may otherwise occur when power is turned on. * Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.
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PACKAGE DIMENSIONS
(Unit : mm) QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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